Testing of metallization networks on insulative substrates supporting semiconductor chips

ABSTRACT

A method for testing the interconnector network on insulative substrates on which integrated circuit chips are to be mounted. The method involves testing for the operability of said interconnector network prior to the mounting of the chips by temporarily mounting at the chip sites a plurality of test chips. Each of these test chips contains a plurality of diodes which respectively connect the chip terminals to a common terminal. The chip terminals are connected to the interconnector network and the common terminal is externally accessible through the substrate. Potential levels are selectively applied to a plurality of test points in the network and differences in potential level between these test points and/or between the points and one or more of the common terminals are determined.

United States Patent [1 1 [1 1 3,746,973 McMahon, Jr. July 17, 1973 [5TESTING OF METALLIZATION 3,609,538 9/1971 Schag 324/66 NETWORKS ONINSULATIVE SUBSTRATES SUPPORTING SEMICONDUCTOR CHIPS [75] lnventor:Maurice T. McMahon, Jr.,

Wappingers Falls, N.Y. [73] Assignee: International Business MachinesCorporation, Armonk, NY. [22] Filed: May 5, 1972 211 A No.: 250,537

[52] US. Cl. 324/51, 324/73 R, 324/158 F [51] Int. Cl G01r 31/02 [58]Field of Search 324/51, 66, 73, 158

[56] I References Cited UNITED STATES PATENTS 1,977,703 10/1934Swartwout 324/54 X 3,192,307 6/1965 Lazar 324/158 F 3,217,244 11/1965Glover 324/54 X 3,405,361 10/1968 Kattner et al. 324/158 P 3,560,9072/1971 Heller 324/158 P Primary Examiner-Gerard R. StreckerAttorney-Julius B. Kraft et a1.

[ 5 7] ABSTRACT A method for testing the interconnector network oninsulative substrates on which integrated circuit chips are to bemounted. The method involves testing for the operability of saidinterconnector network prior to the mounting of the chips by temporarilymounting at the chip sites a plurality of test chips. Each of these testchips contains a plurality of diodes which respectively connect the chipterminals to a common terminal. The chip terminals are connected to theinterconnector network and the common terminal is externally accessiblethrough the substrate. Potential levels are selectively applied to aplurality of test points in the network and differences in potentiallevel between these test points and/or between the points and one ormore of the common terminals are determined.

'7 Claims, 6 Drawing Figures TESTING OF METALLIZATION NETWORKS ONINSULATIVE SUBSTRATES SUPPORTING SEMICONDUCTOR CHIPS BACKGROUND OFINVENTION The present invention relates to the testing of theinterconnector networks on insulative surfaces which are to supportintegrated circuit chips in integrated circuit package units or modules.More particularly, the present invention relates to such high densitymicrominiature packages in which maximum density integrated circuitchips are mounted on insulative substrates as close as possible to eachother to provide a high density package.

With the ever-increasing microminiaturization of integrated circuitchips and packages and the attendant increase in circuit densities perchip and chip densities per insulative substrate or module so that thepresent state of the art is approaching the order of hundreds ofcircuits per chip and tens of thousands of circuits per module,physically accessing test points in not only the chip but even thesupporting substrate for testing purposes is becoming exceedinglydifficult. In the past, it has been conventional practice in testing forthe integrity and operability of interconnector networks on insulativesubstrates, such as modules or boards, to simultaneously contact withtest probe structures all of the test points in the network necessary totest the network for short-circuits or breaks in the interconnectors.However, as a result of the rapid rate of microminiaturization in thisart, the number of chips mounted per unit area of insulative substratehas greatly increased; also, the number of contacts between theinterconnector network and the mounted chips has also greatly increased.Accordingly, the number of test points required to'test theinterconnector network has greatly increased and, more significantly,the density of such contact points per unit area of insulative substratehas also increased many-fold. With this greatly increased density ofrequired test points, physical contact simultaneously with all of thetest'points in the conductive network on an insulative substrate hasbecome impractical. Therefore, there is 'a need in the testing art for amethod of testing the interconnector networks on insulative substrateswhich avoids the simultaneous contacting or probing of all of the testpoints.

SUMMARY OF INVENTION Accordingly, it is a primary object of the presentinvention to provide a method for testing the interconnector network oninsulative substrates to be used in supporting semiconductor integratedcircuit chips which avoids the necessity of simultaneously probing allof the test points in the network.

Another object of the present invention is to provide a method oftesting such interconnector networks wherein the test points can beconveniently contacted physically by test probes.

It is yet a further object of the present invention to provide a methodfor testing of such conductive interconnector networks which permits adetermination to be made as to the integrity and operability of thenetwork prior to the mounting of the integrated circuit chips on thesubstrate.

It is even another object of the present invention to provide anintermediate test structure including the insulative substrate to betested which permits the testing of the interconnector networks withoutsimultaneously probing all of the test points.

The present invention provides a test method for testing the conductiveinterconnector network in the insulative substrate prior to the mountingof the integrated circuit chips which involves temporarily mounting atthe plurality of chip sites at which the chips are to be subsequentlymounted, a plurality of semiconductor test chips. Each of the test chipscomprises a plurality of unidirectional semiconductor devices, e.g.,diodes, each device respectively connecting a terminal of the test chipto a common terminal. Then, by applying selected potential levels totest points in the conductive interconnector network which are connectedto chip terminals and by determining differences in such appliedpotential levels between respective test points and/or between such testpoints and the common terminals, the interconnector network may betested for short-circuits as well as for breaks in the interconnectors.

Preferably, the test chips are mounted on the substrate by fusible metalcontacts between the chip terminals and corresponding interconnectornetworks terminals. Upon the completion of testing, these test chips areremoved from the substrate by fusing such contacts.

Instead of simultaneously contacting all of the test points in theinterconnector network, the present method preferably involvessequentially contacting, with groups of test probes on a test head, thegroups of test points associated with each of the chip sites. These testpoints are preferably arranged around the periphery of the chip site andspaced from the chip.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription and preferred embodiments of the invention as illustrated inthe accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagrammatic fragmentaryplan view of an insulative substrate containing an interconnectornetwork which is to be tested in accordance with the method of thepresent invention; the chips which are to be mounted on the substrateand their chip terminals are shown in phantom.

FIG. 2 is an enlarged diagrammatic fragmentary view of an insulativesubstrate chip site showing the chip to be mounted on the substrate inphantom lines.

FIG. 3 is a cross-section taken along line 3-3 of FIG. 2.

FIG. 4 is a diagrammatic fragmentary view of a chip site on theinsulative substrate similar to the view of FIG. 2 except that a testchip is mounted at the chip site.

FIG. 5 is a cross-section view taken along line 5--5 of FIG. 4.

FIG. 6 is a fragmentary diagrammatic plan view of the insulativesubstrate wherein the test chips are mounted at each of the test sitesand a fragment of the test probe array contacting the test points at oneof the test sites is shown with a portion broken away to expose theunderlying interconnector network.

DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference first to FIGS. 1and 2 in the drawings,

there will now be described an embodiment of the test method of thepresent invention. Insulative substrate 10, which is shown in afragmentary plan view in FIG. 1, comprises an interconnector network 11which interconnects a plurality of integrated circuit chips to bemounted on the substrate. The chips 12, which are shown in phantom line,are mounted at a plurality of chip sites 13 on the surface of substrate10. As an order of magnitude, the structures to be tested comrpise inthe order of 100 chips, approximately 100 X 100 mils, mounted on aninsulative substrate approximately 2 inches X 2 inches in size. Forconvenience in describing the invention, only a few representative chipsites 13 are shown and only a few representative portionsof theinterconnector network 11 are shown. The interconnector network showncomprises inter-chip site connectors 14, as well as intra-chipconnectors 15. The interconnector network may have portions, such asconnectors l4 and 15 (FIGS. 2 and 3), formed on the surface of substrate10, as well as portions, such as intrachip connectors 15A, which areformed below the surface level of substrate 10.

Substrate may be conveniently made of a ceramic material, and in orderto provide portions of the interconnector network, such as A, below thesurface, a multi-level ceramic substrate may be used. Intra-chipconnectors 15 and 15A connect interconnector network terminals16.corresponding to chip terminals 17 and these chip terminals aremounted upon and bonded to the interconnector terminals when theintegrated circuit chip is mounted on substrate 10. Intra-chipconnectors l5 and 15A respectively connect network terminals 16 to anarray of pads 18 which are arranged in groups around the periphery ofeach chip site and are utilized as test points in the subsequent testingof the interconnector network by contacting such test points or pads 18with a plurality of probes. Intra-chip connectors 14 respectivelyconnect pads 18 associated with one chip site with pads associated withanother chip site to form the interconnections between chip sites.

For convenience in illustration, in the structure shown, there areapproximately 50 network terminals 16 associated with each chip siteand, consequently, the chips to be mounted at the site will have 50corresponding terminals; also, 50 test points or pads 18 are associatedwith each chip site. The state of the integrated circuit art has reacheda stage where there would more realistically be one hundred chipterminals and, consequently, one hundred pads 18 per chip site.

Next, with reference to F186. 4, 5 and 6, a plurality of test chips 20are mounted temporarily at each of the chip sites. These test chips havea plurality of terminals 21 which are identical in structure andcoincident with the terminals on the integrated circuit chips which areto be subsequently permanently mounted on the insulative substrate. Inthe illustrative embodiment, because the integrated circuit chips to besubsequently mounted will be joined to the substrate by acontrolledcollapse" technique in which the chip terminals or pads arefused during joining, test chips 20 are joined to the substrate by asimilar technique. This controlledcollapse technique is described indetail in U.S. Pat. No. 3,429,040 and in the article A Critique of ChipJoining Techniques," L. F. Miller, Solid State Technology, April 1970,pp. 50-62. It should be understood, of course, that where the integratedcircuit chips are to be joined to the substrate by other techniques suchas beam lead, ultrasonic bonding or thermocompression bonding which arealso described in the above publication, the test chips would also betemporarily respectively joined to the substrate by such othertechniques.

The structures shown in FIGS. 6, 4 and 5 respectively correspond to thestructures shown in FIGS. 1, 2 and 3 except that the test chips areshown mounted at the chip sites. The test chips comprise a plurality ofdiodes which are shown schematically in phantom lines in FIG. 4.Although only a few of these schematic diodes paths are shown in FIG. 4,there is one such diode path for every chip terminal 21 and,consequently, for every network terminal 16. This diode is formed byhaving a diffused P type region 22 in contact with each test chipterminal 21. The junction between this P type region and the N type bodyof test chip 20 provides a diode path, as shown in FIG. 4, between eachof the chip terminals 21 and common chip terminal 23. Common chipterminal 23 is joined to a corresponding network terminal 24 on thesubstrate which may be externally accessed. In the embodiment shown,such external access is provided by means of pin 25 passing through thesubstrate.

For convenience in illustration, common chip terminal 23, substrateterminal 24 and pin 25 have been shown as being centrally located at thechip sites. This need not be the case. The common terminal may belocated at any point in the chip provided that it is connected to apoint in the substrate which may be externally accessed, either directlyby a pin as shown, or indirectly by an interconnector which runs alongthe insulative substrate 10 to a point which is externally accessed by apin. Since it is customary practice during the operation of theintegrated circuit package to access points in the interconnectornetwork with pins which provide the various power supplies required,such power pins may be conveniently utilized temporarily during testingfor pin 25 to provide external access to the common terminal in thechips.

As previously mentioned, the test chips are mounted temporarily on theinsulatiye substrate 10, as shown in FIGS. 4-6, by a controlled collapsesolder fusion technique as described in U.S. Pat. No. 3,429,040. In FIG.6, only portions of the interconnector network 11 on substrate 10 areshown for convenience in illustration. Actually, the interconnectornetwork 11 is more complex and has many more interconnectors than shown.Also, only a few of the chip terminals 21 and the diode paths to commonterminal 23 are shown; actually, there is such a diode path for each ofthe 50 chip terminals. I

Let us now consider a typical test cycle with reference to FIG. 6. Atester probe head 26 is shown contacting test points 18 at the firstchip site. The structure of the test probe head is merely illustrativeof standard tester probe heads known in the art. The head comprises anarray of probes 27, one for each of the 50 test points 18. The testprobes 27 have been partially broken away so that the interconnectorpattern 11 may be more readily seen. Heat 26 is capable of moving in theX and Y directions. Each of the probes 27 is capable of applyingselected voltages to test points 18 and capable of sensing voltagelevels at these test points. The test probe head is controlled in theconventional manner by computer means, not shown, which have thecapability of applying the voltages to the test points required by thetesting procedure and for receiving and interpreting the data sensed byprobes 27.

In a typical test procedure, a single-test head 26 contacts test points18 associated with each of the test sites in a preselected sequence. InFIG. 6, probe head 26 is shown in contact with test points 18 associatedwith the first of the chip sites. Starting with the first of the fiftytest points which is designated with the numeral 30 in FIGS. 4 and 6,the intra-chip connector connected to point 30 is first tested forcontinuity by applying a voltage level through the test head 26 to onlypoint 30. Then, the voltage drop between point 30 and common point 23 atthe first chip site is determined by sensing the voltage level atexternal pin 25 associated with said first chip site. If intra-chipconnector 15 is complete, there should be substantially little voltagedifference between point and pin 25 because the voltage is applied inthe direction which would maintain the diode path as conductive.

Next, .while still maintaining the same voltage level at point 30, allof the other 49 test points 18 at the first chip site are shortedtogether through the probe head at a lower potential level than point30. The potential level at the other 49 test points is then sensedthrough their respective probes. If any of these other 49 test pointsrises in voltage level approaching that being applied to point 30, thisis an indication that there is in the intra-chip connectors ashort-circuit which permits a path between point 30 and the otherelevated test point other than through the diode array on chip 20. Ifthere are no such short-circuits, the diode path associated with theother 49 test points would be rendered non conductive by such appliedvoltages.

Next, still with respect to the first test point 30, the interchipconnector segment 31, interconnecting the test point 30 with test point32 at a second chip site, is tested in the following manner. An elevatedvoltage level is applied by the probe to only point 30 and the resultingvoltage level at common terminal 33 at the second chip site is sensedthrough the external pin associated with terminal 33. The voltage levelat thisexternal pin should be substantially the same as the voltagebeing applied by the test head to point 30.

Similarly, with the elevated voltage level still applied to test point30, interconnector 34, which connects point 30 to test point 35 at athird chip site, is tested by sensing the voltage level at commonterminal 36 of this third chip site through the pin associated with thiscommon terminal.

Next, with the elevated voltage still applied to test point 30, theinterconnector network must now be tested to insure that there are noshort-circuits between test point 30 and test points at other chipsites. Point 30 is only connected to the second chip site 37 and thethird chip site 38. It is not connected to any of the other chip siteson the insulative'substrate. Therefore, each of the common terminals ateach of such other unconnected chip sites should be at a voltage levelsignificantly different from test point 30. With test point 30 still atits elevated level, the externally accessible pins associated with eachof the common terminals at such other chip sites are sensed. All ofthese pins should be at a voltage level substantially different fromthat of point 30. If any of these pins has a voltage level approachingthat applied to point 30, this is an indication that there is ashort-circuit between point 30 and the chip site of said pin.

The testing of the first point in the test point array associated withthe first chip site is now completed, and with the test head still inthe first position, each of the other 49 test points in the array at thefirst chip site is similarly tested with respect to its intrachipconnections and its inter-chip connections. Upon the completion of thetesting of all of the 50 points at the first chip site, test head 26 isstepped to the next chip site to be tested and the procedure is repeatedfor each of the 50 test points at the second chip site. It should benoted that as the testing progresses, inter-chip connections between atest point in a chip site under test and a test point in a chip sitepreviously tested will have been already tested. In such a case, theprocedure will be skipped with respect to inter-chip connections betweena chip site under test and one previously tested. The computercontrolling the test head may readily keep track of such previouslytested inter-chip connections in any conventional manner.

Accordingly, in the manner described, a single test head which is incontact with a single chip site at any one time is used to test allaspects of the interconnector network on substrate 10 related to saidchip site. This avoids probing of more than one test site with more thanone test head which becomes physically impractical because of increasingchip and test point densities.

Upon the completion of the testing, all of the test chips 20 areremoved. In the embodiment shown, this is accomplished by a removalprocedure which involves melting or fusing terminals 21 which bond thetest chip to the two corresponding terminals in the substrate; there aremany known techniques in the art for removing chips from the insulativesubstrate. Some of these are discussed in general in the above-mentionedpublication, A Critique of Chip-Joining Techniques, by L. F. Miller.Various techniques for chip removal have been described in the art. Forsome examples of such techniques, reference is made to Solder TerminalRework Technique, C. Chiou et al., IBM Technical Disclosure Bulletin,March 1970, page 1,666, Chip Removal by Hot Gas, C. R. Tickner, IBMTechnical Disclosure Bulletin, December 1968, page 875, and LocalizedHeating of Chip Bonding Pad, C. Chiou et al., IBM Technical DisclosureBulletin, January 1967, page 1,051. The chips may be removedindividually from the insulative substrate or they may be removed as agroup by a technique which involves heating and then agitating thesubstrate to, in effect, shake the test chips off the substrate. Aftertesting and removal of the test chips, the integrated circuit chips maybe then mounted at the respective test sites utilizing, in the presentillustrative embodiment, fusible solder techniques as described.Depending on the completeness of the solder removal from the substrateduring the removal of the test chips, some dressing of theinsulativesubstrate may be preferable to remove any of such solder residues priorto the mounting of the integrated circuit chips on the tested insulativesubstrate.

After the removal of the test chips, the actual integrated circuit chipsare permanently joined to the chip sites utilizing the appropriatejoining technique as described above, e.g., controlled collapsetechnique in the present embodiment. The insulative substrate structuredescribed above, which includes an externally accessible pin at eachchip site and an array of test points around the chip site periphery,has a further advantage in performing functional tests on the integratedcircuit chip after the chip is mounted on the substrate. With thisinsulative substrate structure, it is possible to selectively power theintegrated circuit chips one at a time through the external pin whilethe other chips remain off. A test head of the type shown in FIG. 6contacts the test points surrounding the powered chip, and theconventional functional tests are performed upon the chip throughsignals applied to the test points by the head, and the results aresensed in a similar manner.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of the invention.

What is claimed is:

1. In the fabrication of integrated circuit packages wherein a pluralityof semiconductor integrated circuit chips are mounted at a plurality ofchip sites on an insulative substrate having a network of conductiveinterconnectors for interconnecting terminals of said plurality ofchips, a method of testing said conductive interconnector network priorto the mounting of said chips which comprises temporarily mounting at aplurality of said chip sites,

a plurality of semiconductor test chips, each of said test chips havinga plurality of unidirectional semiconductor devices, each devicerespectively connecting a terminal of said chip to a common terminal,

applying selected potential levels to a plurality of test points in theconductive interconnector network connected to said test chip terminals,and

determining differences in potential levels respectively between saidpoints and/or between said points and said c'ommon terminals.

2. The testing method of claim 1 wherein said unidirectional devices arediodes.

3. The testing method of claim 1 wherein said chips are temporarilymounted by fusible metal contacts between terminals on said chip andcorresponding interconnector network terminals, and

upon completion of testing, said temporary chips are removed from saidsubstrate by fusing said contacts.

4. The testing method of claim 1 wherein the group of test pointsrespectively associated with each of the chips and connected to theterminals of said chip are arranged spaced from said chip around theperiphery of the chip site.

5. The method of claim 4 wherein said groups of test points arecontacted with test probes one group at a time, said test probesapplying said selective potential levels to at least one of the testpoints in said groups.

6. The method of claim 5 wherein the connections between the groups oftest points associated with a respective chip and the terminals of saidchip are tested by determining differences in potential levels betweenpoints in said groups contacted by said test probes.

7. The method of claim 5 wherein network interconnections betweenterminals of different chips mounted on said substrate are tested byapplying a potential level to the test point associated with theterminal in the chip being probed which is being connected with aterminal in another chip, and sensing the potential level at the commonterminal in said other chip.

1. In the fabrication of integrated circuit packages wherein a pluralityof semiconductor integrated circuit chips are mounted at a plurality ofchip sites on an insulative substrate having a network of conductiveinterconnectors for interconnecting terminals of said plurality ofchips, a method of testing said conductive interconnector network priorto the mounting of said chips which comprises temporarily mounting at aplurality of said chip sites, a plurality of semiconductor test chips,each of said test chips having a plurality of unidirectionalsemiconductor devices, each device respectively connecting a terminal ofsaid chip to a common terminal, applying selected potential levels to aplurality of test points in the conductive interconnector networkconnected to said teSt chip terminals, and determining differences inpotential levels respectively between said points and/or between saidpoints and said common terminals.
 2. The testing method of claim 1wherein said unidirectional devices are diodes.
 3. The testing method ofclaim 1 wherein said chips are temporarily mounted by fusible metalcontacts between terminals on said chip and corresponding interconnectornetwork terminals, and upon completion of testing, said temporary chipsare removed from said substrate by fusing said contacts.
 4. The testingmethod of claim 1 wherein the group of test points respectivelyassociated with each of the chips and connected to the terminals of saidchip are arranged spaced from said chip around the periphery of the chipsite.
 5. The method of claim 4 wherein said groups of test points arecontacted with test probes one group at a time, said test probesapplying said selective potential levels to at least one of the testpoints in said groups.
 6. The method of claim 5 wherein the connectionsbetween the groups of test points associated with a respective chip andthe terminals of said chip are tested by determining differences inpotential levels between points in said groups contacted by said testprobes.
 7. The method of claim 5 wherein network interconnectionsbetween terminals of different chips mounted on said substrate aretested by applying a potential level to the test point associated withthe terminal in the chip being probed which is being connected with aterminal in another chip, and sensing the potential level at the commonterminal in said other chip.